Signaloid, a computing platform company providing hardware and binary-translation-based acceleration of AI, robotics, aerospace, and quantitative finance workloads, announced the tapeout and preliminary specifications documents for its C0-ASIC. Delivery of engineering samples to the first customer is due in Q3 2026 and additional FPGA-based systems implementing the ASIC’s design are under discussion for deployment in the UK and Switzerland later in 2026.

The C0-ASIC was targeted specifically at energy-efficient physical AI workloads. The UK Advanced Research and Invention Agency (ARIA) will take delivery of systems based on the ASIC for use in next-generation AI workloads such as second-order methods.

“The Scaling Compute program at ARIA commissioned several innovative technology prototypes pursuing unconventional ideas to design new AI accelerators,” says ARIA Program Director Suraj Bramhavar. “We commissioned Signaloid’s C0-ASIC for evaluation in randomised numerical linear algebra and probabilistic computing workloads. We believe randomised linear algebra represents a fundamentally new and powerful technique underpinning many applications in computer science, including AI, and exploiting these principles in hardware could provide an entirely new vector for improved performance. We are excited to invest in this theme, in partnership with Signaloid, to explore its full potential.”

The C0-ASIC implements Signaloid’s distribution-extended compute hardware (UxHw) technology.

Unlike conventional CPUs and GPUs, which use impressive amounts of sheer computational force across thousands of compute cores to solve problems that require iterative randomised variations, Signaloid’s UxHw builds on new mathematical techniques to restructure computations, dynamically, to achieve the same results while often using 1000-fold (or more) less energy.

The UxHw technology and its implementation are covered by a growing portfolio of over 90 intellectual property filings in the US, China, Taiwan, Japan, and the EU.