NVIDIA has announced collaborations with Cadence Design Systems and Synopsys to optimise critical electronic design automation (EDA) applications for the NVIDIA Vera CPU, aiming to accelerate semiconductor design workflows for next-generation CPUs, GPUs and AI systems.

The company said it is already deploying the Vera CPU across its own EDA workflows used to develop future generations of processors, demonstrating how high-performance CPU architecture can improve some of the industry's most demanding engineering workloads.

As AI models and advanced processors become increasingly complex, semiconductor companies are spending years validating chip behaviour, identifying design flaws and refining architectures before manufacturing. While GPUs and AI have accelerated several stages of chip development, key EDA workloads—including logic simulation, formal verification and digital implementation—continue to rely heavily on CPU performance.

According to NVIDIA, early testing of production-class workflows showed that the Vera CPU delivered up to 1.5 times higher performance on selected workloads when running leading EDA applications from Cadence and Synopsys.

Among the evaluated tools was Cadence Jasper, a formal verification platform that combines intelligent proof technologies with machine learning to detect and resolve design bugs early in the development cycle. NVIDIA also tested Synopsys VCS, a functional verification solution widely used to simulate and validate complex semiconductor designs before fabrication. Both applications achieved performance improvements of up to 1.5x using the same number of CPU cores.

Beyond benchmark performance, NVIDIA said it is working closely with both EDA software providers on application profiling, software optimisation and system-level tuning to further improve engineering productivity across a broader range of chip design workflows.

The collaboration reflects the growing importance of CPU performance in AI-driven semiconductor development, where faster simulation and verification can shorten design cycles, accelerate product tape-outs and support the rapid development of next-generation AI infrastructure.